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This application claims priority to U. Provisional Patent Application No. Various embodiments of the present disclosure relate generally to digital data processing and, more particularly, to a clock recovery, a clock and data recovery CDRa receiver, and a communication system for multiple data channels.

Unless otherwise expressly indicated herein, the materials described in this section are not necessarily prior art to the subject matter disclosed in this application and, therefore, should not be regarded as admitted prior art against the disclosures of the present application.

For example, when a digital data stream is transmitted to a receiver without a clock signal, the receiver may use a CDR technique to generate a clock based on a proximate value of frequency reference. Finding the clock signal may enable the data to be recovered.

However, some problems exist with traditional CDR techniques. For example, many CDR techniques require phase locking of a data stream clock recovery from random binary signals each channel. This may have the effect of subjugating the operation of rest of the streams to the locked data stream. Parallel communication techniques have also been developed to transfer data using a plurality of data channels simultaneously in order to provide high speed transmission.

Accordingly, there may exist a need for more efficient CDR techniques for multiple data streams. To attain the advantages and in accordance with the purpose of the present disclosure, one aspect of the present disclosure may provide a clock recovery apparatus for a plurality of data channels. The apparatus may comprise a plurality of channel blocks, each channel block comprising a frequency detection block configured to generate an intermediate signal based on a respective data signal received from a respective data channel and a clock recovery from random binary signals signal, and a recovery block configured to recover a clock signal for the respective data channel in response to the respective data signal and the global signal.

The apparatus may also include a global signal generation block configured to receive and combine the intermediate signals from the plurality of channel blocks to generate the global signal. According to another exemplary aspect, the frequency detection block in each channel block may comprise a reference signal generator configured to generate a reference signal based on the respective data signal, a feedback signal generator configured to generate a feedback signal based on the global signal, and a frequency detector configured to generate the intermediate signal representing a frequency difference between the clock recovery from random binary signals signal and the feedback signal.

In some exemplary aspects of the present disclosure, a clock recovery apparatus for a plurality of data channels may comprise a frequency acquisition block configured to receive data signals from a plurality of data channels and generate a global signal based on at least one data signal received from one or more active channels of the plurality of data channels, wherein the global signal has a frequency substantially the same as the frequency used by the one or more active channels.

The apparatus may also comprise a plurality of recovery blocks corresponding respectively to the plurality of data channels, each of the plurality of recovery blocks clock recovery from random binary signals configured to recover a clock signal for a corresponding data signal by rotating the phase of the global signal based on the corresponding data signal. Another exemplary aspect of the present disclosure may provide a receiver for a plurality of data channels.

The receiver may comprise a plurality of channel blocks, each channel block comprising a frequency detection block configured to generate an intermediate signal in response to a respective data signal received from a respective clock recovery from random binary signals channel and a global signal, and a recovery block configured to recover a clock signal and data for the respective data channel in response to the respective data signal and the global signal. The receiver may also comprise a global signal generation block configured to receive and combine the intermediate signals from the channel blocks to generate the global signal.

Some exemplary aspects may provide a communication system comprising the above-described receiver. Some exemplary aspects may provide a method for clock recovery for a plurality of data channels. The method may comprise performing, at an apparatus comprising at least two channel blocks and a global signal generation block, generating, using a frequency detection block at each channel block, an intermediate signal based on a respective data clock recovery from random binary signals received from a respective data channel and a global signal, recovering, using a recovery block each channel block, a clock signal for a respective data channel in response clock recovery from random binary signals the respective data signal and the global signal, and, at the global signal generation block, receiving and combining the intermediate signals from each channel block clock recovery from random binary signals generate the global signal.

One exemplary aspect of the present disclosure may also provide a tangible computer-readable medium containing instructions. The instructions may be configured to, when executed by an apparatus containing at least one processor, at least two channel blocks, and a global signal generation block, perform a method for clock recovery for a plurality of data channels.

The method may comprise generating, using a frequency detection block at each channel block, an intermediate signal based on a clock recovery from random binary signals data signal received from a respective data channel and a global signal, recovering, using a recovery block each channel block, a clock signal for a respective data channel in response to the respective data signal and the global signal, and receiving and combining, using the global signal generation block, the intermediate signals from each channel block to generate the global signal.

Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments consistent with the invention, and, together with the description, serve to explain the principles of the invention. In the following detailed description, reference is made to the accompanying drawings, which form a put hereof. Whenever possible, the same reference characters are used throughout clock recovery from random binary signals drawings to refer to the same or like parts, unless context dictates otherwise.

The disclosed embodiments will be mainly described hereinafter with respect to a clock recovery architecture. However, it will be apparent to those skilled in the art that the disclosed embodiments are not limited to this type of architecture.

In case a reference clock signal is not present, a. VCO may need to be phase locked to a data stream in one of the channels e. As shown in FIG. The active data channels may include channels from which valid data signals, such as non-return-to-zero NRZ signals, are received. Global signal generation block may include an oscillator controller and an oscillator By way of example only, this division ratio may be In one exemplary embodiment, oscillator controller may include a combiner and a loop filter Loop filter may be configured to filter the output of combiner to generate oscillator control signal OC.

In some exemplary embodiments, each channel block may contain a stochastic reference clock generator SRCGa CID tolerant counter-based frequency detector FDand a jitter suppression loop. The SRCG may create a quasi-periodic signal through the division of random input data, which may be a data signal. The outputs of the FD in each channel block may be combined and accumulated in the digital domain for controlling a global VCO.

Thus, the VCO clock recovery from random binary signals be frequency-locked, provided that an input signal is present in any one of the data channels which endows a master-less and reference-less operation. Entire data channels may operate independently without requiring a master channel while achieving low power and area overhead. A SRCG-based frequency acquisition scheme may consume significantly less power compared to conventional designs since the SRCG may require a single line rate D flip-flop and the entire remaining blocks operate at divided rates.

Thus, in some exemplary embodiments, an additional jitter suppression loop with an adjustable frequency divider may be employed in each channel to counter-balance any accumulated jitter caused clock recovery from random binary signals the SRCG and suppress the jitter from the VCO. The VCO signal frequency locked to the SRCG may be distributed to each CDR channel, and the phase rotator may be controlled to minimize the phase difference between the input data signal and the clock signal.

Large low frequency phase noise of the SRCG can be reduced by preventing the clock recovery from random binary signals of its period jitter. The division ratio in the SRCG may then be adjusted dynamically. Such variable frequency division concept may be commonly employed in frequency synthesizers. In case the clock edge of the SRCG output is lagging the target edge, the division ratio of the SRCG may be reduced to shorten the period of the subsequent.

On the contrary, the division ratio may be increased in case the clock edge of the SRCG leads the target edge. A bang-bang phase detector may be utilized to control the division ratio of the SRCG. The amount of variable division ratio chosen to balance jitter accumulation and the self jitter generation of the SRCG.

The accumulation jitter may be modeled by a random walk process, and an adjustable frequency divider may be represented as a phase domain addition. The output jitter of the loop may be given by. By taking the bi-linear transformation of this equation for simplicity, the output jitter may be represented as. In case K bpd is less than 1, jitter accumulates at the output and the low frequency output phase noise is greater than that at the input.

The mean and variance of the time difference between two adjacent transition edges of the SRCG is given by. The output of the phase rotator may be used as a reference clock in the jitter suppression loop. The reduction of the accumulated jitter of the SRCG suppresses the low frequency phase noise of the FLL and eventually makes the rotator output clock even cleaner.

Simulated phase noise of the SRCG and the FLL with and without the jitter suppression loop clearly shows the effectiveness of the proposed scheme. The exemplary embodiments illustrated above may be applied to various receivers including devices for optical, wired, or wireless communication. The device may include network equipment, personal devices, computers, and modules, such as bus interfaces in computers.

Receiver may further include data processing block Data processing block may be configured to apply further processing to the recovered data. The processing may include various processing dedicated to the various receivers illustrated above. Various embodiments of the receiver illustrated above may be applied to various communication systems, including communication systems in which remote transmitter and receiver perform optical, wired, or wireless communication and inter module communication in which modules in a device e.

In the exemplary embodiments disclosed above, any of the operations, processes, and steps can be implemented as computer-readable instructions stored on a tangible computer-readable medium. However, those skilled in the art will recognize that some aspects of the embodiments disclosed herein, in whole or in part, can be equivalently implemented in integrated circuits, as one or more computer programs running on one or more computers e.

The present disclosure is not to be limited in terms of the particular embodiments described in this application, which are intended as illustrations of various aspects.

Many modifications and variations can be made without departing from its spirit and clock recovery from random binary signals, as will be apparent to those skilled in the art. Functionally equivalent methods and apparatuses within the scope of the disclosure, in addition to those enumerated herein, will be apparent to those skilled in the art from the foregoing descriptions.

Such modifications and variations are intended to fall clock recovery from random binary signals the scope of the appended claims.

The present disclosure is to be limited only by the terms of the appended claims, along with the full scope of equivalents to which such claims are entitled. Disclosed are various exemplary embodiments of a clock recovery apparatus for recovering clock signals of multiple data channels. In clock recovery from random binary signals exemplary embodiment a clock recovery apparatus for a plurality of data channels clock recovery from random binary signals include a plurality of channel blocks, where each clock recovery from random binary signals block may include a frequency detection block configured to generate an intermediate signal based on a respective data signal received from a respective data channel and clock recovery from random binary signals global signal, and a recovery block configured to recover a clock signal for the respective data channel in response to the respective data signal and the global signal.

What is claimed is: A clock recovery apparatus for a plurality of data channels, the apparatus comprising: The apparatus of claim 1wherein: The apparatus of claim 1wherein the global signal generation block comprises: The apparatus of claim 3wherein the oscillator controller comprises: The apparatus of claim 3wherein the recovery block in each channel block comprises: The apparatus of claim 5wherein the rotation controller in each channel block comprises: The apparatus of claim 7wherein: The apparatus of claim 9wherein the global signal generation block comprises an oscillator controller configured to combine the intermediate signals to generate an oscillator control signal; and.

The apparatus of claim 9wherein each of the recovery blocks comprises: US USB2 en Methods clock recovery from random binary signals multi-channel data detection phase locked loop frequency error combination. Technique to reduce clock recovery clock recovery from random binary signals modulation in high-speed serial transceiver. Arrangement for reproducing n digital signals from n adjacent tracks on a record carrier. An arrangement for reproducing n clock recovery from random binary signals signals from n adjacent tracks on a recording medium.

Common state-space multi-channel digital sample timing phase control of multiple read channels for correlated signals. Methods and systems for delay compensation in global PLL-based timing recovery loops. Clock and data recovery circuitry with auto-speed negotiation and other possible features. Phase interpolation-based clock and data recovery for differential quadrature phase shift keying.

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Fusion de opciones sobre acciones definicion

A phase detector and method therefor , includes a first flip-flop for sampling an incoming data signal in accordance with a first local clock signal to produce a first sampled data signal, a second flip-flop for sampling the incoming data signal in accordance with a second local clock signal to produce a second sampled data signal, and a third flip-flop for sampling the second sampled data signal, as based on the first sampled data signal, to produce a binary control signal.

The third flip-flop comprises a double-edge flip-flop. The present Application is related to the following co-pending application:.

The present invention generally relates to data transmission and communication systems, and more particularly to tri-state phase detectors used in a clock recovery system for recovering a clock signal from transmitted NRZ non-return-to-zero random data.

The phase detector of the present invention provides the retimed or regenerated data directly from the transmitted NRZ data utilizing the recovered clock signal. The phase detector concept of the present invention can be used either to recover a full-rate clock or a half-rate clock.

When data are transmitted over a communication link, the associated clock signal is generally not transmitted, thereby providing for better efficiency of the link. The clock signal also provides timing necessary for subsequent digital circuitry such as demultiplexers or framers.

Therefore, transmission systems generally require that the clock signal at the receiving end of the link somehow be extracted from the incoming data signal. In the conventional systems, two main techniques are usually used for clock recovery. These two approaches are direct extraction techniques and phase-locked loop PLL techniques.

In a direct extraction scheme, a high Q bandpass filter is required, among other circuits. However, these high Q bandpass filters are generally expensive and limit the link to work only at a single data rate. Also, direct extraction techniques are difficult to integrate therein.

In that case, phase shifters are used to ensure adequate alignment between the extracted clock and the received data. This alignment is temperature- and process-dependent and will vary depending on the circuitry used. In PLL techniques, a reference clock is generated at the frequency or sub-frequencies of the received data rate, usually using a voltage-controlled oscillator VCO.

A phase detector PD circuit compares the phase angle between the VCO clock signal and the received data stream. The phase detector provides a control signal which is a function of the relative phase between the VCO clock signal and the received data signal.

This control signal is used to adjust the VCO frequency until the clock signal is synchronized with the received data.

The PD is a key circuit for clock and data recovery applications using PLL techniques, especially when the timing becomes critical as the data rate increases. As frequencies become higher, time delays inherent in digital circuits become more significant compared to the bit interval. The bit error rate BER of a transmission system e. To ensure optimum bit error rate when sampling the received data with the extracted clock for data regeneration, it is desirable to sample at the midpoint of each bit interval.

At very high clock frequencies e. Two main classes of PD circuits, linear PDs and binary PDs, are commonly used in clock and data recovery applications.

Linear PDs may not work well at extremely high bit rates because they must generate relatively narrow pulses compared to the bit interval as the phase error becomes smaller.

Also, the static phase error of the data recovery loop using a linear PD may be relatively large, because of unbalanced loading and delay mismatch for example, which is not desirable for optimum sampling of the received data. A desirable feature is to have the retiming of the data function as part of the PD operation itself. In this case, no external adjustment of the clock and data alignment is required to accommodate process, temperature and power supply variation and aging as well, since the PLL will act in such a way that the clock will stay aligned with the data.

Another desirable feature is to enable a high impedance state, or a tri-state output, indicating that transitions are missing in the received random data stream. This high impedance state will minimize VCO frequency drift by holding its frequency control input voltage constant during periods of missing transitions in the incoming data stream.

In turn, this will reduce the jitter generation or phase noise due to VCO frequency drift and will help prevent unlocking of the PLL. For very high transmission data rates in particular, complex data and clock distribution should be avoided. The parasitic elements associated with interconnect wires cause loading and coupling effects that degrade the frequency behavior and the noise performance of the circuits.

Latency has a direct impact on the jitter generation of a PLL, and should be as small as possible to reduce output jitter.

Finally, because transmission data rates are increasing rapidly, PLL circuits using VCOs running at a sub-harmonic of the data rate are often used to enable application of existing technologies with limited frequency performance. A half-rate VCO, which runs at a frequency equal to half the data rate, is often chosen as it represents a good compromise between performance and complexity as opposed to a full-rate VCO, which runs at a frequency equal to the data rate.

In summary, it is highly desirable that PDs used for clock and data recovery applications have the following features:. One very common full-rate bang-bang tri-state PD is described by J.

In this approach, three samples of the data are taken using data latches: The PD output signal is generated by comparing these samples using logic gates. For that approach, a minimum of 4 logic gates plus 8 data latches are required. Therefore, the total gate count is 12, with the clock being distributed to 8 data latches. The propagation delay of this PD is equal to 1 clock cycle plus 3 gate delays. A half-rate bang-bang tri-state phase detector is described by M.

The present authors have used the concept of the full-rate PD described above modified for half-rate operation. Simple and efficient PDs such as the one described in the present invention, having all the seven features listed above, have significant advantage, especially when targeting high transmission data rates.

The present invention, which addresses the needs identified in the conventional techniques, provides an efficient tri-state PD having a bang-bang type of operation preferably used for clock and data recovery applications. Since the data recovery function is part of its operation, this PD has a self-correcting clock and data alignment, which maintains sampling at the optimum sampling point regardless of process fabrication spread or power supply and temperature variations.

The concept of this PD is an extension of the one described in the above-listed copending application, which is hereby incorporated herein by reference. In comparison to the Alexander full-rate bang-bang tri-state PD mentioned above, the full-rate PD version of the present invention requires a minimum total gate count of 9 8 data latches and one XOR gate , with the clock signal being distributed to 6 data latches only.

The propagation delay can be as low as 1 clock cycle plus 2 gate delays. The Reinhold PD described above uses 16 data latches and 10 logic gates with a clock loading of 10 data latches.

Its propagation delay is at least equal to 1 clock cycle plus 4 gate delays. In comparison, the half-rate PD version of the present invention requires a total gate count of 12 with a clock loading of 5 data latches. The propagation delay is reduced to half a clock cycle and 2 gate delays.

In a first embodiment of the invention, the PD includes a first and second Edge-Triggered Data Flip-Flop ETDFF for sampling an incoming data stream with a first and second clock signal, respectively, to produce a first and second sampled data signal, respectively.

A third ETDFF is used to sample the first sampled data signal with the first clock signal to produce a third sampled data signal. The M-DETDFF operates similarly to a classical double-edge-triggered data flip-flop which transfers its input to its output on each transition of the sampling signal. However, in contrast to the classical double-edge-triggered data flip-flop, the M-DETDFF alternatively transfers its input to its output on one sampling edge, and the complement of its input to its output on the other sampling edge.

The PD of the present invention is optimized to be used for clock and data recovery using the phase-locked loop PLL technique. The first and second clock signals have the same frequency and the first clock signal is half a bit of the incoming data stream time earlier than the second clock signal.

The first and second sampled signals are identical, but are shifted from one another by half a bit time. The sign of this shift depends on the position of the first and second clock edges e. Because the second sampled signal is sampled using the first sampled signal, the M-DETDFF output is thus a binary signal or a bang-bang signal which state indicates whether the incoming data stream is leading or lagging the clock signal.

The incoming data stream may include long series of consecutive identical bits, in which case the output of the M-DETDFF is not valid anymore since it continues to hold its previous state in the absence of transitions. Consequently, a transition detector is required. The first and third sampled signals are taken from the incoming data stream, with the third sampled signal one bit time ahead of the first sampled signal. Consequently, the first and third sampled signals will be different each time a transition occurs in the incoming data stream.

Thus, an XOR gate applied to the first and third sampled signals can be used to sense the presence of data transitions. A PD that produces this kind of output information is known as a tri-state PD. The propagation delay of the XOR gate should closely match the clock to data output propagation delay of the M-DETDFF in order to synchronize the data transition detection with the phase comparison. In a second embodiment of the invention, instead of using a XOR gate as a transition detector, the first and third sampled signals are subtracted from each other and the resulting fourth sampled signal, instead of the first sampled signal, is used to sample the second sampled signal.

Consequently, each time transitions in the incoming data stream are present, the fourth sampled signal will toggle between two states. When a transition in the incoming data stream is missing, the value of the fourth sampled signal is zero, and will remain zero until the next transition happens. If differential architecture is used to implement the PD, then no additional gate is required to subtract the first and third sampled signals since the complementary signals are readily available.

When the present invention is used for clock and data recovery using the phase-locked loop technique, then under locked conditions, the sampling edges of the second clock signal are automatically aligned with the edges of incoming data stream. Thus, the sampling edges of the first clock signal are automatically aligned at the middle of each data bit of the incoming data stream, and thus the first and third sampled signals correspond to the recovered or regenerated data.

Thus, the data recovery is fully part of the PD operation and the optimum sampling point is automatically maintained regardless of technology process spread or power supply and temperature variations.

The PD of the present invention has a simple architecture with a low gate count. This in turn reduces the physical implementation complexity. Moreover, the clock and data loading is low. Also, the latency of the PD of the present invention is reduced as a result of the low gate count. To achieve the above, in a first aspect of the present invention, a phase detector and a method , includes a first flip-flop for sampling an incoming data signal in accordance with a first local clock signal to produce a first sampled data signal, a second flip-flop for sampling the incoming data signal in accordance with a second local clock signal to produce a second sampled data signal, and a third flip-flop for sampling the second sampled data signal, as based on the first sampled data signal, to produce a binary control signal.

The third flip-flop preferably includes a double-edge flip-flop. The foregoing and other purposes, aspects and advantages will be better understood from the following detailed description of preferred embodiments of the invention with reference to the drawings, in which:. Referring now to the drawings, FIG. The PD includes a plurality e. M-DETDFF operates in a similar way as a classical double-edge-triggered data flip-flop which transfers its input to its output on each transition of the sampling signal.

Instead of transferring its input on each sampling edge, however, the M-DETDFF alternatively transfers its input to its output on one sampling edge, and the complement of its input to its output on the other sampling edge.

An example of such a circuit is given in FIG. The first clock signal is also applied to the clock input C of the third ETDFF , thereby sampling the signal PD is optimized to be preferably used in a receiver of a transmission system to recover the clock signals and from the signal using the phase-locked loop technique.

The signal is in this case a random data stream. In the rest of the description, the signal refers to a random data stream which is preferably NRZ Non-Return-to-Zero coded and will be referred to as data It is noted that PD is optimized if the clock signals and have preferably exactly the same frequency, the clock signal being preferably half a data bit time late compared to the clock signal The data bit time preferably is equal to half of the smallest period presents in the signal.

The rate of data preferably is equal to the inverse of a bit time.